1. Field of the Invention
The present invention relates to a semiconductor device whose internal power supply voltage is generated by a voltage step-up circuit, and more specifically to a semiconductor device whose internal power supply voltage is generated by a voltage step-up circuit with a plurality of stepped-up levels.
2. Description of Related Art
When an external power supply voltage VDD is lowered, an internal power supply voltage VPP is stepped-up by a three-times voltage step-up circuit. A technology is known that application of an internal power supply voltage VPEQ, which is lower than the internal power supply voltage VPP, to part of a circuit that is supplied with the internal power supply voltage VPP reduces the power consumption. Here the internal power supply voltages VPP and VPEQ are higher than the external power supply voltage VDD; and the internal power supply voltage VPEQ is lower than the internal power supply voltage VPP.
FIG. 4 is a block diagram showing a structure of a conventional three-times voltage step-up circuit (VPP voltage step-up circuit) 120. With reference to FIG. 4, the VDD supply circuit 111 supplies a voltage VDD to a node B while a node A is at a low level. The VDD supply circuit 111 steps up a potential of the node B by separating the node B from the VDD supply circuit 111 before the node A becomes a high level. A VSS supply circuit 112 supplies a voltage VSS while the node B is supplied with the voltage VDD. The VSS supply circuit 112 separates a node C from the VSS supply circuit 112 at the same time when the node B is separated from the VDD supply circuit 111. The VPP latch circuit 113 supplies the voltage VDD to a node D while the node C is supplied with the voltage VSS. A VPP latch circuit 113 separates the node D from the VDD supply circuit 111 at the same time when the node C is separated from the VSS supply circuit 112, so that the VPP latch circuit 113 supplies an electric potential of node D, which is stepped up by connecting the node C with the node B, to a terminal VPP.
FIG. 5 is a block diagram showing a structure of a conventional two-times voltage step-up circuit (VPEQ voltage step-up circuit) 110. The VPEQ latch circuit 114 in FIG. 5 supplies a voltage VDD to a node B while the node A is at a low level. A VPEQ latch circuit 114 separates the node B from the VDD supply circuit 111 before the node A becomes a high level, so that the VPEQ latch circuit 114 supplies a stepped up potential of the node B to a terminal VPEQ. A two-times voltage step-up circuit is employed as the VPEQ voltage step-up circuit 110. The VPEQ latch circuit 114 transfers a potential of the node B stepped up by a pump capacitor (capacitor) between the node A and the node B to the terminal VPEQ when the node B is kept higher than or equal to VDD by the VPEQ latch circuit 114 and the node A oscillates with an amplitude VDD. These operation timings are controlled by the pulse signal B and the pulse signal D.
The VPP voltage step-up circuit 120 comprises a VDD supply circuit 111 and a VSS supply circuit 122. The VDD supply circuit 111 keeps the node B at a potential higher than or equal to VDD. The VSS supply circuit 112 draws down the electric potential of the node C to VSS. The VPP latch circuit 113 draws down the level of the node D, stepped up by the two-stage pump capacitors (capacitors) between the node A and the node B and between the node C and the node D, to VPP when the node A oscillates with the amplitude VDD. These operation timings are controlled by pulse signals A to C and E. Here, the pulse signals are adjusted to maximize gain of the internal power supply.
The patent document 1 describes a voltage generation circuit comprising a capacitor that is commonly used as both a pumping capacitor in a first voltage generation circuit for generating a first voltage and a pumping capacitor in a second voltage generation circuit for generating a second voltage. The voltage generation circuit described in the Patent Document 1 reduces its layout area because the circuit generates the first voltage and the second voltage by the single pumping capacitor.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-151279A